The present invention relates to apparatus and method for decoding a coded digital signal and, more particularly, to apparatus and method for decoding and error correcting a coded digital video signal having error correction data added thereto reproduced from a record medium, e.g., a compact disk.
As is known, moving pictures, i.e., motion video, is digitized, encoded and recorded at a variable rate on a record medium in accordance with various video standards, for example, the MPEG (Moving Pictures Expert Group) standard. The MPEG standard calls for three types of encoded pictures: intra-encoded pictures (I pictures or I-frames); forward predictive-encoded pictures (P pictures or P-frames); and bidirectionally predictive-encoded pictures (B pictures or B-frames). A combination of these three types of pictures form what is known as a group of pictures or a GOP. Although the MPEG standard also generally is applied to audio (e.g., voice) data, other forms of encoding, for example, ATAC (Additive Transform Acoustic Coding), are also used to digitize and compression-encode voice data.
Referring first to FIG. 1, a data reproducing apparatus 1 for reproducing data at a variable rate from a compact disk is shown. Data reproducing apparatus 1 includes a pickup device 3 which provides a laser beam onto an optical disk 2 to reproduce the data recorded thereon in a manner well known in the art. Pickup device 3 supplies a reproduced signal S1 to a demodulating circuit 6 included in a demodulating system 5 which is controlled by a system controller 4. The reproduced signal S1 is demodulated and supplied via a sector detector circuit 7 to an ECC (error correction code) circuit 8 which detects and corrects errors in the supplied signal. Sector detection circuit 7 detects new sectors in the reproduced signal, but if a sector number or address is not detected, a sector number error signal is supplied to a track jump determination circuit 9. Similarly, an error signal is supplied to track jump determination circuit 9 if ECC circuit 8 detects an uncorrectable error in the signal.
ECC circuit 8 detects an d correct s errors in the supplied data in a manner to be discussed and supplies the error corrected data to a ring buffer memory 10 which stores the data at addresses therein in accordance with a write pointer WP supplied from a ring buffer control circuit 11. Memory 10 also reads the data stored therein from addresses in accordance with a read pointer RP supplied from control circuit 11. As is well known, control circuit 11 generates the write addresses (write pointer WP) from sector signals supplied from sector detection circuit 7 and generates the read addresses (read pointer RP) in response to control signals supplied by system controller 4 and a code request signal R10 supplied from a data separating circuit 13.
Ring buffer memory 10 supplies the data stored therein to a header separation circuit 14 in data separation circuit 13 which separates a pack header from each pack of data supplied thereto and also separates a packet header from each packet contained in the data, and the separated headers are supplied to a separation circuit controller 15. Circuit controller 15 supplies a switcher control signal to a switching circuit 16 to cause video data supplied to input terminal G to be supplied via terminal H1 to a video code buffer 17, and to cause audio data supplied to input terminal G to be supplied via terminal H2 to an audio code buffer 19. Stream identification information (stream ID) included in the headers identify the type of data (e.g., video or audio) included in the packets.
Video code buffer 17 stores the supplied video data therein and generates and supplies a code request signal R1 to data separation circuit 13 in accordance with the amount of data that is stored in buffer 17. Video code buffer 17 outputs to a video decoder 18 the stored data in response to a code request signal R1' supplied from video decoder 18. Video decoder 18 decodes the read video data to produce a digital video signal and supplies the digital video signal as an output at output terminal OUT1.
Similarly, audio code buffer 19 stores the supplied audio data therein and generates and supplies a code request signal R2 to data separation circuit 13 in accordance with the amount of data that is stored in buffer 19. Audio code buffer 19 outputs to an audio decoder 20 the stored data in response to a code request signal R2' supplied from audio decoder 20. Audio decoder 20 decodes the read audio data to produce a digital audio signal and supplies the digital audio signal as an output at output terminal OUT2.
As previously mentioned, demodulating system 5 demodulates the reproduced signal S1 by means of demodulating circuit 6. Demodulating circuit 6 converts signal S1 that is supplied from pickup device 3 to a binary signal using the well-known RF processing so as to detect an EFM+ synchronization pattern (e.g., 8, 16 conversion). A "rough" servomechanism based on the constant linear velocity (CLV) method operates on signal S1 based on detected synchronization patterns. Then, after sector detection circuit 7 detects an EFM+ sync header in signal S1, a PLL (Phase Locked Loop) servomechanism operates on the sync header, and when several sync headers are continuously detected by detection circuit 7, data S2 supplied from detection circuit 7 is deinterleaved in ECC circuit 8.
Referring to FIG. 2, a block diagram of ECC circuit 8 is shown, in which ECC circuit 8 is comprised of four random access memories, RAM 24, RAM 26, RAM 28 and RAM30, and three error correction code (ECC) decoders 25, 27 and 29. As will be discussed, decoders 25, 27 and 29 detect and correct errors in data S2 using the three error detection/correction sequences data C11 (also known as the first C1 sequence), data C2, and data C12 (also known as the second C1 sequence) which includes C1/C2 convolutional Reed-Solomon codes (i.e., CIRC Plus codes). The data sequences are included in the EFM+ demodulated data S2. Data S2 is supplied to RAM 24 which stores the data therein in the address order of 00, 01, . . . , A8, and A9 (called herein as an "EFM+ Write"), and after two frames of S2 data are stored in RAM 24, RAM 24 supplies the first-stored frame of data to decoder 25 from the address order of 00', 02', . . . , A8', 01, 03, . . . , A9 (called herein as a "C1 read") so as to de-interleave the C1 sequence of data, such as shown in FIG. 3. Decoder 25 receives the read-out data and corrects errors in the S2 data by identifying the error positions and correction patterns of the data, reading the erroneous data from RAM 24 (i.e., the C1 read), exclusively logically adding the read data to the correction patterns, and writing the resultant data to RAM 26 (called herein as a "C1 Write"), such as shown in FIG. 4. Decoder 25 decodes the C1 sequence of data (and thus error detects/corrects the S2 data) over the C2 code sequence length.
After C1 sequence data is decoded (over the entire C2 code sequence length), the C2 sequence of data is then "ECC" decoded. The data stored in RAM 26 is read therefrom at the address order of 00', 01', 02', 03', . . . , A9' (called herein as a "C2 read") and the read-out data is supplied to decoder 27 which subsequently decodes the read-out C2 sequence of data. Decoder 27 generates an "uncorrectable error" flag for each frame of data that is uncorrectable and supplies the uncorrectable error flag to decoder 29 in synchronism with the supply of the decoded S2 data so as to allow the uncorrectable data to be erased (i.e., removed) from the data stream. Error detection/correction in decoder 27 is similar to that of decoder 25, and a C1 uncorrectable error flag is generated when data is uncorrectable.
After decoder 27 decodes the data using the C2 data, the decoded data is stored in RAM 28 (called herein as a "C2 Write"), such as shown in FIG. 5. Thereafter, RAM 28 reads the data including the C12 sequence of data stored therein from the address order of 00', 01, 02, 03, . . . , A9 (called herein as a "C12 read") and supplies the read-out data to decoder 29. Similar to the C2 uncorrectable error flag, a C12 uncorrectable error flag is generated and utilized for the purpose of erasing (i.e., removing) uncorrectable errors based on the C12 sequence of data. Decoder 29 error detects/corrects the data (using the C12 data) and stores the data in RAM 30 in the order of 00, 01, 02, 03, . . . , A9 (called herein as a "C12 write"), such as shown in FIG. 6. The data stored in RAM 30 is read therefrom in the order of 00, 01, 02, 03, . . . , A9 (called herein as an "OUT read"), descrambled and supplied to ring buffer memory 10, as previously discussed.
Storage addresses RA at which data are stored are generated from the following equations and using a data order Dn in the direction of the C1 data and the frame numbers Fn in "C1 code units" that are based on the data addresses of RAMs 24, 26, 28, and 30, such as shown in FIG. 7. All numbers in the equations hereinafter are in hexadecimal notation.
Dn: data No. (00-A9) PA1 Fn: frame No. (00-B9) PA1 RA: RAM address (0000-7FFF) EQU Fna=Fn+46+01 EQU IF (ECC MODE=C2), Fna=Fna+Dn EQU IF (Fna&gt;FF), Fna=Fna+46-100 (1) EQU (Dn=00) AND (00&lt;Dn&lt;80) EQU RA=(Fna).times.80!+Dn 6:0! (2) EQU (Dn=80) AND (80&lt;Dn&lt;A0) EQU RA=(Fna+18).times.20!+Dn4:0! (3) EQU (Dn=A0) AND (80&lt;Dn&lt;AF) EQU RA=(Fna+BA-100).times.10!+Dn3:0! (4)
As previously discussed, the CIRC Plus code is error detected/corrected decoded utilizing decoders 25, 27, and 29 which decode the C11, C2, and C12 sequences of data, respectively, and the resultant decoded data are reordered in RAMs 26, 28, and 30. However, since the timing for outputting the error-corrected data is not fixed, two counters are needed to provide for the transfer of the data and for the correction of the errors, which results in an unnecessarily complicated structure. Furthermore, using three separate memory devices, i.e., RAMs 24, 26 and 28, to separately decode the C11, C2, and C12 sequences of data results in an undesirable large memory storage capacity.
Referring to FIG. 8A, timing diagrams for several different signals are shown. If a single memory device is utilized to transfer two frames of C11 data within one clock period of a read frame clock (signal RFCK in FIG. 8A), then two separate frame counters are required to perform the separate functions of transferring data and correcting errors. Still further, separate frame counters also are required when data is transferred and when errors are corrected even if the clock is output only during data transfers, such as shown in FIG. 8B.